Si4430/31/32-B1
Rev 1.1
35
Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is not available
in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data rate, and thus
cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming data.
One advantage of this mode that it saves a microcontroller pin because no TX Clock output function is required.
The primary disadvantage of this mode is the increase in occupied spectral bandwidth with FSK (as compared to
GFSK).
Figure 13. Direct Synchronous Mode Example
Figure 14. Direct Asynchronous Mode Example
4.2.2.3. Direct Mode using SPI or nIRQ Pins
In certain applications it may be desirable to minimize the connections to the microcontroller or to preserve the
GPIOs for other uses. For these cases it is possible to use the SPI pins and nIRQ as the modulation clock and
data. The SDO pin can be configured to be the data clock by programming trclk = 10. If the nSEL pin is LOW then
the function of the pin will be SPI data output. If the pin is high and trclk[1:0] is 10 then during RX and TX modes
the data clock will be available on the SDO pin. If trclk[1:0] is set to 11 and no interrupts are enabled in registers 05
or 06h, then the nIRQ pin can also be used as the TX/RX data clock.
The SDI pin can be configured to be the data source in both RX and TX modes if dtmod[1:0] = 01. In a similar
fashion, if nSEL is LOW the pin will function as SPI data-in. If nSEL is HIGH then in TX mode it will be the data to
mC
DATACLK
MOD
nRES
MOSI
MISO
SCK
nSEL
nIRQ
Direct synchronous modulation. Full
control over the standard SPI & using
interrupt. Bitrate clock and modulation
via GPIOs.
GPIO configuration
GP0 : power-on-reset (default)
GP1 : TX DATA clock output
GP2 : TX DATA input
DataCLK
MOD(Data)
VDD_RF
TX
RXp
RXn
SCLK
SDI
SDO
VDD_DIG
NC
NC
Matching
mC
MOD
nRES
MOSI
MISO
SCK
nSEL
nIRQ
Direct asynchronous FSK modulation.
Modulation data via GPIO2, no data
clock needed in this mode.
GPIO configuration
GP0 : power-on-reset (default)
GP1: not utilized
GP2 : TX DATA input
MOD(Data)
VDD_RF
TX
RXp
RXn
SCLK
SDI
SDO
VDD_DIG
NC
NC
Matching
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